1. Field of the Invention
The present invention relates generally to electronic components and systems for receiving data, and more particularly relates to systems and components which convert serial data pattern signals, transmitted or suitable for transmission over a high-speed synchronous serial transmission media to parallel pattern output signals.
2. Description of the Related Art
Many devices, including standard telecommunication interface devices such as universal asynchronous receiver transmitters (UARTs) and modems, employ asynchronous parallel input/output (I/O) criteria to simplify their internal architecture and permit high speed operation. It is often necessary to transfer or transmit parallel I/O to, from and/or between such devices. One method in current use is to employ parallel cable as the transmission media, where each conductor of the cable is dedicated to one of the parallel inputs or outputs. This arrangement has proven to be unsatisfactory, particularly as line length and number of inputs and outputs increases because of wiring interconnect hardware requirements increased conductor count, increased cost and poor reliability.
Furthermore, parallel format message traffic and control information travelling between host systems (e.g. between two microprocessors) typically each occupy individual conductors of a parallel cable even though this nonhomogeneous type of parallel data run at different data rates. This further increases hardware requirements which has a negative impact on both reliability and cost.
It has been recognized that multiplexing nonhomogeneous parallel data and converting the multiplexed data to serial format for transmission over a single serial interface is desirable to reduce the aforementioned problems and allow for greater distances between communication nodes.
Devices are known and in use which permit asynchronous parallel I/O to be interfaced with a serial communications link. The known methods and apparatus fall into two broad categories, those using asynchronous serial interfaces and those using synchronous serial interfaces.
The asynchronous serial interfaces are difficult to work with because each byte of data communicated over the media must be resynchronized, limiting maximum data rate. Existing synchronous serial interfaces, for example, on Universal Synchronous Asynchronous Receiver Transmitters (USARTs), are problematic because they require synchronizing data. This data can be supplied by a host system or the interface device, and is usually specified by an interface protocol. This represents an added constraint when designing a parallel/serial interface rendering the interface "nontransparent" to the designer.
In addition to the aforementioned problems the multiplexing and demultiplexing of nonhomogeneous parallel data for serial transmission is typically performed external to an interface device. These external processes further increase system complexity, cost and nontransparency by virtue, of the need to insert additional hardware between the host system and the interface device. Further complications in known systems which multiplex data sources from several sending systems over the same wire (typical in tri-state bus architectures in computer systems) are the need for bus controller/arbitrators, software resources, and line drivers that can be switched on and off.
Finally, many commercially available UARTs, USARTs, modems, etc. have eight bit data inputs and outputs. It is somctimes desirable to transmit and/or receive longer data patterns which then require either special purpose hardware or the sending of several "words" to pass the pattern.